The new ASIC will integrate both the transmit and receive processing of hiSky’s core MODEM technology within a compact CSP single-chip solution. This will enable substantially higher volumes of Smartellite™ terminals to be manufactured with unprecedented commercial applicability. Using a proven 55 nm wafer technology process, the new ASIC MODEM-on-chip is capable of delivering a throughput of between 6kbps and 20kbps for voice and IoT use-cases as per the ESA SVNO program.
Looking further than the ESA funded SVNO program, hiSky will develop inside this ASIC the capabilities that allow up to 10Mbps for more data-hungry applications; over both geostationary satellites or low-earth-orbit satellites, such is its versatility.
The MODEM-on-chip ASIC shall have a very low power consumption of less than 1.5W and low cost to meet the price for the mass market needs.
hiSky expect the first ASIC tape-out to be completed by mid-December 2020. The first sample chips will be available by February 2021. This is in line with ESA milestone commitments and allows hiSky to stay on-track for program completion in 2022.
Mr. Philip Meyers, General Manager hiSky UK said, “We are delighted to be progressing to the development of our ASIC MODEM-on-chip. Taking hiSky’s cutting edge terminal designs and combining them with an ASIC MODEM-on-chip will allow us to produce the highest quality products at high volumes, all while maintaining a price-point that provides access to satellite communications and remote IoT for the mass market.
The ASIC MODEM is a hugely important element in our ARTES SVNO project with the European Space Agency, and I’d like to take this opportunity to once again thank ESA for their support, guidance and experience in this process.”